1. Field of the Invention
This invention relates generally to multi-chip modules and, more particularly, to a technique for fabricating an embedded chip substrate.
2. Description of the Related Art
Conventional high density interconnect (HDI) processes often use cavities formed into a substrate base for the placement of chips so that the top surfaces of the chips are essentially planar with the surface of the substrate. The substrate is generally a ceramic or a composite structure. The conventional HDI technique for fabricating cavities in the substrate is to mechanically machine or mill out the cavity material with a computer-controlled diamond tooled bit. This time consuming process does not always provide the desired chip cavity depth and can result in cracks which render the substrate unusable.
In the conventional HDI process, chips are placed into cavities on multiple drops of die attach adhesive for mechanical, thermal, and electrical mounting. Chips placed with this process can be displaced during further processing because there are non-uniform surface tension forces at the chip-to-die attach adhesive inter-face. This displacement reduces precision in chip location, and further processing steps are required to adapt each electrical interconnection to the chip misalignment. Furthermore, a moat (gap) is present between each chip and the walls of its respective well.
In conventional HDI techniques, an adhesive-coated polymer film overlay covers a plurality of integrated circuit chips in chip wells on an underlying substrate. The polymer film provides an insulated layer upon which is deposited a metallization pattern for interconnection of individual circuit chips. Methods for performing a HDI process using overlays are described in Eichelberger et al., U.S. Pat. No. 4,783,695, issued Nov. 8, 1988, and in Eichelberger et al., U.S. Pat. No. 4,933,042, issued Jun. 12, 1990, both of which are hereby incorporated by reference. Additionally, it is desirable to provide via openings or apertures in the polymer film overlay so as to be able to provide electrical connection between various parts of a chip or between several chips. Eichelberger et al., U.S. Pat. No. 4,894,115, issued Jan. 16, 1990, which is hereby incorporated herein by reference, discloses embodiments for providing such apertures. Furthermore, methods for gaining access to and replacing a defective integrated circuit chip are disclosed in Eichelberger et al., U.S. Pat. No. 4,878,991, issued Nov. 7, 1989, and Wojnarowski et al., U.S. Pat. No. 5,154,793, issued Oct. 13, 1992, which are hereby incorporated by reference.
The presence of moats surrounding the chips in conventional substrates may cause thinning of the adhesive of the polymer film at the chip perimeters and sagging of the polymer film over the moats, thus adding difficulty in placing vias and patterning interconnects close to the chip wells. Additionally, mismatches between the coefficients of thermal expansion of ceramic substrates and polymer overlays sometimes induce stress at the adhesive layer, thus tending to promote separation of the polymer film from the substrate.
Eichelberger, U.S. Pat. No. 5,091,769 issued Feb. 25, 1992, describes an integrated circuit package formed by placing integrated circuit chips backside down on a substrate, encapsulating the faces and sides of the chips, fabricating vias and interconnections through the encapsulant to the contact pads for testing and burn in procedures, and removing the encapsulant after testing. When chips of differing thicknesses are used in a single multi-chip module (MCM), their pads are not situated in a common plane, so this method requires either that some of the chips be thinned or that the vias be of varying depths. Additionally, this technique involves a step of mechanical grinding for planarizing the surface and the use of an encapsulant material which is removed after testing.
Aforementioned Fillion et al., application Ser. No. 08/087,434, discloses a method of fabricating an HDI substrate by molding plastic around chips placed on a film, thus eliminating the milling process and providing a planar surface without moats between chips and the substrate. Briefly, the technique includes applying an insulative base sheet over a base. At least one chip having contact pads is placed face down on the base sheet. A mold form is positioned around a desired perimeter and surrounds at least one chip. Substrate molding material is added and then hardened within the mold form. Then the mold form and base are removed, the substrate is inverted, and the chips are interconnected.
It would be desirable to have a plastic molding process in which the mold form becomes an integral part of the substrate that protects the substrate from exposure to chemicals. Additionally, it would be desirable to have a process in which the substrate can be kept in the same orientation throughout the process of molding and chip interconnection.